Automatic encoder test set for pcm encoders



ErAL 3,154,738

AUTOMATIC ENCODER TEST SET FOR PCM ENCODERS Filed Nov. 9, 1961 Oct. 27,1964 P. J. GREENE. JR..

2 Sheets-Sheet l By R.E.y4EGE/? ATTORNEY Oct. 27, 1964 P. J. GREENE,JR.. ETAL 3,154,738

AUTOMATIC ENCODER TEST SET FOR PCM ENCODERS Filed Nov. 9, 1961 o, F/G.4

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L55 53 AND NOT R J. GREENtjJR. /NVEN Tons 0. L. W/LL /AMS By R. E. VA EGER ATTORNEY United States Patent Oitice Patented Oct. 27, 1964 l.Greene, Er., Plaistow, N-l., and @wen L. er, and Robert E. raeger,Topsiield, Bell Te aborato ies,lncor vnone t N13., a corporation of NewYork No 9, i963, Ser. No. rSLS Claims, CL S25-41) This invention relatesgenerally to systems that employ pulse code modulation (PCM) principles.lt specifically concerns devices for testing the performance of PCMencoders.

As is well known an n-digit PCM encoder is a device whose function is toconvert an input signal sample into binary code form. Such an encoder inidealized form is capable of generating 2n distinct output code signalsto represent 2rl equally divided amplitude levels of the input signal.iractical encoders, however, do not perform in such ideal fashion asthey frequently do not provide a distinct code output for 2 equallydivided input levels. Often the input signal levels are divided on anunequal basis and it is therefore necessary to measure the variance ofan encoder from the ideal.

ln the past the determination of the decision levels of an encoder wasobtained by applying a variable directcurrent voltage to the input tothe encoder, and recording the voltages at which the output codechanges. The results obtained were then plotted to obtain an indicationof the variance of the decision levels of the encoder from the ideal.This technique required 2n measurements for an iz-digit encoder, and inaddition to being a long and tedious task (128 separate measurements ina seven-digit encoder) this technicue is essentially a static one whichdoes not include stray etlects usually found by dynamic operation of theencoder, and a aster and more accurate technique is desirable.

Accordingly, it is an object of this invention to substantially shortenthe time required to measure the deviation of an encoder from an idealencoder.

Lt is a related object of this invention to eliminate the inaccuraciesof measurement found in the prior art, by dynamically testing theencoder and thereby including dynamic stray eli'ects in the measurement.

ln accordance with this invention a PCM encoder is dynamically tested byhaving it continuously encode known voltages and comparing the resultingcode output signals with the output of a code generator which issynchronized to the source ot known voltages and produces binary codewordl outputs corresponding to the idealized decision levels oi theencoder corresponding to the amplitudes of the known voltages,

in one embodiment of the invention the encoder encodes the outputvoltage of a linear ramp voltage source and the resulting digital codeoutput is compared with the output of a binary word generator. Thebinary word generator generates binary code words which are synchronizedto the source of ramp voltage so that the code output or the wordgenerator represents the amplitude of the output voltage of the rampvoltage source. The outputs of the encoder and the word generator arecompared on a digit-by-digit basis and an error output signal isgenerated whenever they differ.

rlfhe invention will be more fully comprehended from the followingdetailed description talten in conjunction with the drawings, in which:

l is the input-output characteristic of an ideal encoder;

FlG. 2 is a likely-input output characteristic of a practical encoder;

FIG. 3 is a block diagram of an encoder test set embodying theinvention;

PEG. 4 is a block diagram of the word generator shown in FIG. 3;

FG. 5 is a block diagram of the linear ramp generator shown in FIG. 3;and

FlG. 6 is a block diagram of the comparator circuit shown in PEG. 3.

An idealized n-digit encoder has an input amplitude range of 2n equallydivided amplitude levels, and in respouse to an input signal a discretecode output representative of the amplitude of that signal is produced.In response to an input signal whose amplitude is that of the lowestlevel, represented by the region between the ordinates O and l on thevertical axis of the encoder characteristic shown in FIG. l, a codeoutput which represents the number zero in binary form is produced. Whenthe input amplitude level is equal to or greater than the ordinate l theencoder produces a code output representing in binary form the numberone. Between the ordinates l and 2 the encoder will produce a binarycode output representing the number one, but when the input ampiitudeexceeds a value represented by ordinate 2 the encoder will produce acode output which in binary form represents the number two. This processof encoding results in an ideal encoder having a so-called staircasecharacteristic which is shown in FIG. 1. Each so-called step of thecharacteristic has the same height as every other step because the idealencoder generates a distinct code output representing a given inputlevel whenever the input signal is equal to that level or greater thanit by an amount no greater than a step.

Uur rtunately practical encoders are unable to achieve the perfectiondepicted in PEG. l, since they are not always capable of producing theproper code output in respouse to a particular level of the inputsignal. rEhe result of such a deviation from the ideal is showngraphically in lilG. 2 where the innut-output characteristic of atypical practical encoder is shown. Here the failure to produce theproper output code as above described resul ts in an input-outputcharacteristic having steps which vary considerably in height. rThus inthe characteristic shown in FlG. 2 the encoder erroneously produces anoutput representing the number one when the input signal is considerablybelow the first ordinate on the vertical axis. Similarly, a code outputrepresenting the number two will be produced by an input signal whoseamplitude is less than the second ordinate, while a code representingthe third ordinate will not be produced until the amplitude of the inputsignal is almost equal to an amplitude represented by the fourthordinate on the vertical axis.

As discussed above, the input-output characteristics of an encoder weredetermined in the past by applying a variable direct-current voltage tothe input oi the encoder and measuring the input signal amplitudes atwhich the encoder output code change. This was essentially a statictechnique which did not take into account stray effects usuallyencountered in the dynamic operation of the encoder, and, in addition,was a slow and tedious process. ln accordance with this invention, anencoder is tested by comparing its code output in response to a knowninput signal with an artificially generated standard which issynchronized to the known input signal, and a test circuit embodyingthis invention is shown in FlG. 3. Here a source 19 of a linearlyincreasing voltage is applied to an encoder 11 to be tested. The source1l) produces a linear ramp voltage whose initial amplitude correspondsto the amplitude for which an ideal encoder of the type under test willgenerate `a code output which in binary form represents `the numberZero. The maximum voltage generated by source 10 corresponds to thatamplitude for which an ideal encoder of the type under test Willgenerate a binary code output which represents the number 2n. A standardcode is artificially generated by word generator 12 and the output ofthe encoder in response to the voltage from source 10 is compared withthe output of the word generator 12. The word generator 12 is a suitablytriggered binary counter which produces x word code repetitions: i.e.,it repeats code zero'x times, code one x times, code two x times, and soforth, until code 2n has been repeated x times. The number f times, xeach code is repeated may be any number. The Word generator 12 and thelinear ramp generator are synchronized and the magnitude and frequencyof the ramp generator output adjusted to cause the output code of theencoder to agree with the code of the Word generator 12 at the initialand maximum voltages of generator 1f). With the end points synchronizedin this fashion the encoder has (x)2n word times to go through the 2ndecision levels and it must therefore repeat the code for each inputlevel x times. The encoder and the word generator are mutuallycontrolled by a digit pulse generator 13 which in turn is controlled bya source of clock pulses 14.

The digit code output of the encoder 11 and word generator 12 areapplied to a comparator 15 which produces an output everytime theoutputs of the encoder and the Word generator disagree. The encoderunder test is considered to be satisfactory or not satisfactory for theparticular use for which it is planned in accordance with the number oferrors committed in each x word code repetition. The errors occurringduring each x word code are counted by error counter 16 which is resetat the end of each x Word code repetition. When the encoder has produceda number of errors during an x word code repetition in excess of thatnumber considered to be such that the encoder is not suited for aparticular use reject indicator 17 produces an indication of that fact.

The operation of the encoder test set generally described above is moreeasily explained by considering a specific example. Consider, forexample, the testing of a seven-digit encoder. Such an encoder producesa code Word output occupying 8 time slots with the last seven time slotsrepresenting the input :signal amplitude in binary code form. The firsttime slot of the last seven represents the most significant digit andthe last time slot the least significant digit. The encoding of thesignal in the seven time slots is governed by seven digit control pulsesD2 through D8 which govern the weighing of the sample against thereference standards. These digit control pulses appear on separatecontrol lines from digit generator 13 during the second through eighthtime slots first while a digit control pulse D1 serves to reset theencoder to code another sample and provides an empty eighth time slotbetween code Words.

To test such a seven-digit encoder a word generator 12 shown in blockdiagram form in FIG. 4 is employed. Here eleven binary counters 21through 31 are connected together so that a change in state of apreceding counter triggers the succeeding counter. The input to thefirst binary counter 21 is connected to the output terminal of dlgrtgenerator 13 on which digit control pulse D1 appears. As a result, aninput pulse is applied to the first binary counter 21 at the beginningof each word of the encoder and, as a result, counter 21 changes stateseight times during each word output of the encoder. Since bmary counters22 through 30 are connected to their lmmediately preceding counters sothat they change states every other time the preceding counter changesStates it 1s apparent that binary counter 24 changes states every eightword times of the encoder. Similarly, binary counter 25 changes sta-tesevery sixteen word times and so forth through binary counter 39. As aresult if the state of binary counter 24 is considered to represent theleast significant digit of a seven-digit code and the states of thesucceeding counters through counter 30 to represent increasinglysignificant digits then counters 24 through 30 form a counter Whoseoutput states in response to pulse D1, if made to appear during theseventh through second time slots, respectively, of a code word,represent the binary codes of the numbers zero through 127 repeatedeight times each (x=8). The appearance of the states of the binarycounters 24 through 30 :at the proper times is assured through the useof AND gates 34 through 4) which apply the output voltages of counters24 through 30, respectively, to output terminal 41 by means of OR gate42. The gates 34-40 are rendered conductive at the proper times sincethe opening of the gates is controlled by digit control pulses D8through D2, respectively.

The output of binary counter 30 is connected to the input or" binarycounter 31 which is not used to provide any portion of the `standardcode output but is used to synchronize the word generator 12 to thelinear ramp generator. After code numbers zero through 127 have eachbeen generated eight times (x=8) binary counter 31 changes states andthis transition is applied as a synchronizing signal to the input of avoltage time base generator 10 shown in FIG. 5. Generator 10 may be anyhighly linear voltage ltime base generator and a suitable one is shownon page 213 of Pulse and Digital Circuits by Millman and Taub, publishedby lvicGraw-I-Iill Book Company, 1956. The initial output voltage isadjusted by means of a source 46 of bias voltage which is adjusted sothat the initial voltage applied to the encoder 11 is of that amplitudefor which the encoder should generate the output code for the numberzero. The frequency of operation of the generator 1li is adjusted sothat at the end of 128 eight word time repetitions the voltage appliedto the encoder 11 is equal to that amplitude for which the er1- codershould generate the output code for the number 127. Between these twopoints of voltage the generator 10 generates a linearly increasingvoltage, and during the 8(128) word times following the generation of avoltage for which the encoder should produce the code for number 127 theoutput voltage from generator 10 is retraced in response to the changeof state of binary counter 31. Thus error counting is done on everyother 1024, 8(128) word rate.

The comparator circuit 15 is shown in block diagram form in FIG. 6. Thefunction of this circuit is to produce an output pulse whenever the codeword output from the encoder 11 under test and the code word output fromthe word generator 12 differ. The output of the encoder is applied to anencoder `blocking oscillator 5f) which produces an output pulse onoutput terminal 51 in response to an input pulse from the encoder 11 andproduces a negative voltage on output terminal 52 in response to aninput pulse. When in a given time slot the encoder produces a space theencoder blocking oscillator 50 produces zero voltage on output terminal51 and a positive voltage on output terminal 52. Word generator blockingoscillator 53 produces corresponding outputs at output terminals 55 and54 in response to the input signal from the word generator 12. Thus whenthe Word generator 12 produces an output pulse a positive voltageappears at terminal 55 and zero voltage at terminal 54, and when nopulse is produced by the word generator 12 during a given time slot zeroVoltage is .present at 'terminal 55 and a positive voltage is present atterminal 54.

Blocking oscillators 50 and 53 are turned off in accordance with turnolf pulses derived from the clock pulses, at the end of each time slot.The clock source 14 is also applied to a pulse generator circuit 56which produces a very narrow output pulse centered in time in the middleof each time slot in response to the clock pulses from clock source 14.

It is the func-tion of AND-NOT gate 58 to check for the commission ofpulses by the encoder during no pulse time. Terminal 51 of blockingoscillator 50 is connected to one input of AND-NOT gate 58 and terminal54 of word generator blocking oscillator 53 is connected to the NOTinput of AND-NOT gate 58. The output of pulse generator 55 is applied tothe third input terminal of AND-NOT gate 53 so that during the presenceof a pulse output from pulse generator 56- an output pulse appears atoutput terminal S9 of AND-NCT gate 58 when a positive voltage is presenton terminal S1 and a positive voltage is present on terminal 54. Theoutput of AND-NST gate 53 will produce no output signal in the event apulse is present on terminal 5l and zero voltage is present on terminal54 which is the condition indicating that the encoder and word generatorhave both produced an output pulse in a given time slot and that theyare in agreement. Thus in the event the encoder has produced a pulse andthe word generator has not produced a pulse an output pulse will bepresent at terminal 59 indicating that the encoder 11 has committed anerror in erroneously producing the output pulse.

Whereas AND-NOT gate 58 checks for the commission of pulses during nopulse time, it is the function of AND- NOT gate ou to check for theomission of pulses during a pulse time. Here terminal 52 of the encoderblocking oscillator Sti is used to inhibit AND-NOT gate so t there Willbe no output present on terminal Gil of l Whenever encoder blockingoscillator generates a positive voltage in response to the encoder ill.Gate will, however, generate a pulse in the absence of such a conditionprovided a pulse from pulse generator is present and a positive voltageis present on terminal $5 indicating that the Word generator blockingoscillator has generated a pulse in response to the generation of apulse by the Word generator 12. It should be understood that the rolesof the word generator and encoder blocking oscillator inputs arereversed in gate 6d as compared to gate 5S. A pulse is present at theoutput of gate if there is a pulse from pulse generator 5u and a pulsefrom the Word generator and not an encoder pulse. in gate 53, however, apulse is generated if there is a pulse from generator Sti and there isan encoder pulse and not a Word generator pulse.

The outputs of AND-NOT gates 58 and 6@ are gated through an 0R gate d2to nre a blocking oscillator o3 called the digit error blockingoscillator. Blocking oscillator 63 generates an output pulse for everydigit error, and this output pulse is applied to a bistable circuit @ito cause it to change states. The bistable circuit ed is called a Wordrate iiip-iiop and is set to one of its stable conditions by theapplication of digit pulse El and is caused to change states upon theoccurrence of an output pulse from digit error blocking oscillator 63.The application of additional output pulses from blocking oscillator f3before the Word rate ip-op is reset by control pulse Dfi does not causeit to change states again and thus during each word, ip-iiop 64 can onlyproduce one output pulse to indicate that one or more errors have beencommitted during the eight time slots comprising a Word.

The error counter 16 is a series of binary counters whose function is tocount the number of errors produced during each eight word interval inwhich a given sainple is applied to the encoder 11 and in whichgenerator 12 generates a binary number representative of that sample.The counter 16 is reset at the end of each eight word interval by thechange of state of binary counter 23 in the Word generator circuit 12Whose output changes at that time. The binary counters of counter i6 areserially connected so that the first counter is initially set upon theoccurrence f the iirst input pulse, the second counter upon theoccurrence of the second input pulse, the third counter upon theoccurrence of the fourth input pulse, and so forth, in accordance withthe usual techniques for binary counting. If it has been predeterminedthat the encoder does not perform satisfactorily if four or more errorsoccur during any eight Word interval than a three stage counter is usedWith the output generated by the third counter upon the occurrence ofthe fourth error used to trigger a reject indicator circuit i7 whichindi- Cates that the encoder does not meet specifications. rl`he rejectcircuit may be any alarm, light or buzzer, and so forth. Should theencoder be considered to fail to meet specifications in the event two ormore errors are committed during an eight word interval then the counter16 may comprise only two binary counters With the output of the secondcounter in response to the second input pulse used to indicate afailure. Other methods of counting the number of errors during an eightword interval may be employed to trigger the reject indicator after anypredetermined number of errors.

Thus in accordance with this invention the encoder is tested Whileactually encoding input signals with the accuracy of the encodermeasured by comparing its digital output and an artificially generateddigital signal standard. This measuring technique includes stray effectspresent only when the encoder is operating at its normal rate, and inaddition is much faster than the technique employed in the prior art.

lt is to be understood that the above-described arrangements areillustrative of the application of the invention. There is, for example,no necessity for limiting the input to the encoder 11 to a linearlyincreasing voltage and source 10 could be any other type of voltage.Source l@ could be, for example, a source of sinusoidal voltage and theWord generator 12 would then generate a digital sine Wave in order totest the encoder. ln addition, the number of times (t) that each codeWord is repeated by Word generator 12 is completely free of limitation.Finally, when the particular encoder under test does not provide a timeslot separation between Words then each Word comprises n time slotsinstead of n-j-l time slots and each word repetition occurs in x02) timeslots. Numerous other arrangements may be devised by those skilled inthe art Without departing from the spirit and scope of the invention.

What is claimed is:

l. A test circuit for testing the performance of a PCM encodercomprising, in combination, a PCM encoder to be tested having an inputterminal and an output terminal, a source of varying voltage connectedto the input of said encoder, a binary code word generator synchronizedto said source of voltage to generate a series of binary code wordoutput signals corresponding to the respective input signal amplitudesto said encoder, and means to compare the code signals produced at saidencoder output terminal in response to said source voltage and therespective binary code Words generated by said generator to produce anerror signal when said code signals differ from the code words.

2. A test circuit for testing the performance of an n-digit PCM encodercomprising, in combination, an n-digit PCM encoder having an inputterminal to which signal amplitude samples to be encoded are applied andan output terminal at which n-digit binary codes occupying n-successivetime slots and representing said signal amplitude samples are produced,a source of linear ramp Voltage connected to said input to said encoder,a binary code Word generator to generate n-digit binary code Wordssynchronized to said source of linear ramp voltage so that said codeoutput of said generator represents the amplitude of stud output voltageof said linear ramp voltage source during each n-digit time interval,means to compare the code signals produced at said encoder output inresponse to said linear ramp voltage and said code output of said binaryWord generator on a digit-bydigit basis and to generate a digit erroroutput signal Whenever the code signals differ in any time slot, andmeans responsive to said digit error signals to generate a single Worderror output signal in response to one or more digit error signalsoccurring in a given n-digit word.

3. A test circuit for testing the performance of an n-digit PCM encodercomprising, in combination, an n-digit PCM encoder having an inputterminal to which signal amplitude samples to be encoded are applied andan output terminal at which n-digit binary codes occupya ingn-successive time slots and representing said signal amplitude samplesare produced, a -source of a linear ramp voltage connected to said inputto said encoder whose initial output voltage is equal to that voltage atwhich said encoder should ideally generate the binary code number zeroand whose maximum output voltage is equal to that voltage at which saidencoder should ideally generate the binary code number 2-1, a binarycode word generator to generate n-digit binary code Words synchronizedto said source of linear ramp voltage so that said code output of saidgenerator represents the amplitude of said output voltage of said linearramp voltage source during each n-digit time interval, means to comparethe code signals produced at said encoder output in response to saidramp voltage and said code output of said binary work generator on adigit-by-digit basis and to generate a digit error output signalwhenever said outputs differ in any time slot, and means responsive tosaid digit error signals to generate a single word error output signalin response to one or more digit error signals occurring in a givenn-digit Word, and means responsive to a given number of Word erroroutput signals to indicate that the encoder under test does not meetpredetermined requirements.

4. A test circuit for testing the performance of an n-digit PCM encodercomprising, in combination, an n-digit PCM encoder having an inputterminal to which signal amplitude samples are applied and an outputterminal at Which an n-digit binary code occupying n-successive timeslots representing said signal amplitude sample is produced, a source ofa linear ramp voltage connected to the input to said encoder Who-seinitial output voltage is equal to that voltage at Which said encodershould ideally generate the binary code number zero and whose maximumoutput voltage is equal to that voltage at which said encoder shouldideally generate the binary code number ZTI- 1 with the frequency ofrepetition of said output voltage of said ramp generator equal to (Jc)2ntime slots, where x is a predetermined number, a binary code wordgenerator to generate n-digit binary codes and synchronized to saidsource of linear ramp voltage to generate x identical binary wordsduring each x(n-i-1) time slots to represent the amplitude of said rampgenerator during successive x(n}1) time slots, means to compare the codesignals produced at said encoder output in response to said ramp voltageand said code output of said binary code word generator on adigit-by-digit basis and to generate a digit error output signalWhenever said output-s diler in any time slot, and means responsive to4said digit error signals to generate a single word error output signalin response to one or more digit error signals occurring in a givenn-digit word, and means responsive to a given number of Word erroroutput signals in x(1t{l) successive time slots to indicate that thcencoder under test does not meet predetermined requirements.

5. A test circuit for testing `the performance of an n-digit PCM encodercomprising, in combination, an ndigit PCM encoder having an inputterminal to which signal amplitude samples are applied and an outputterminal at which an n-digit binary code occupying n-successive timeslots representing said signal amplitude sample is produced, a source ofa linear ramp voltage connected to the input to said encoder Whoseinitial output voltage is equal to that voltage at which said encodershould ideally generate the binary code number zero and Whose maximumoutput voltage is equal to that voltage at which said encoder shouldideally generate the binary code number 2n-1 with the frequency ofrepetition of said output voltage of said ramp generator equal to (x)2Iltime slots, Where x is a predetermined number, a binary code wordgenerator to generate n-digit binary codes and synchronized to saidsource of linear ramp voltage to generate x identical binary wordsduring each x(n) time slots to represent the amplitude of said rampgenerator during successive x(n) time slots, means to compare the codesignals produced at said encoder output in response to said ramp voltageand said code output of said binary code word generator on adigit-bydigit basis and to generate a digit error output signal Wheneversaid outputs differ in any time slot, and Vmeans responsive to saiddigit error signals to generate a single Word error output signal inresponse to one or more digit error signals occurring in a given n-digitword, and means responsive to a given number of word error outputsignals in x(n) successive time slots to indicate that the encoder undertest does not meet predetermined requirements.

Hess et al June 18, 1957 Mann Oct. 9, 1962

1. A TEST CIRCUIT FOR TESTING THE PERFORMANCE OF A PCM ENCODERCOMPRISING, IN COMBINATION, A PCM ENCODER TO BE TESTED HAVING AN INPUTTERMINAL AND AN OUTPUT TERMINAL, A SOURCE OF VARYING VOLTAGE CONNECTEDTO THE INPUT OF SAID ENCODER, A BINARY CODE WORD GENERATOR SYNCHRONIZEDTO SAID SOURCE OF VOLTAGE TO GENERATE A SERIES OF BINARY CODE WORDOUTPUT SIGNALS CORRESPONDING TO THE RESPECTIVE INPUT SIGNAL AMPLITUDESTO SAID ENCODER, AND MEANS TO COMPARE THE CODE SIGNALS PRODUCED AT SAIDENCODER OUTPUT TERMINAL IN RESPONSE TO SAID SOURCE VOLTAGE AND THERESPECTIVE BINARY CODE WORDS GENERATED BY SAID GENERATOR TO PRODUCE ANERROR SIGNAL WHEN SAID CODE SIGNALS DIFFER FROM THE CODE WORDS.